Fast and effective techniques for T-count reduction via spider nest identities
In fault-tolerant quantum computing systems, realising (approximately) universal quantum compu- tation is usually described in terms of realising Clifford+T operations, which is to say a circuit of CNOT, Hadamard, and π/2-phase rotations, together with T operations (π/4-phase rotations). For many error correcting codes, fault-tolerant realisations of Clifford operations are significantly less resource-intensive than those of T gates, which motivates finding ways to realise the same transfor- mation involving T -count (the number of T gates involved) which is as low as possible. Investigations into this problem [3–6, 13, 21] has led to observations that this problem is closely related to NP-hard tensor decomposition problems  and is tantamount to the difficult problem of decoding exponen- tially long Reed-Muller codes . This problem then presents itself as one for which must be content in practise with approximate optimisation, in which one develops an array of tactics to be deployed through some pragmatic strategy. In this vein, we describe techniques to reduce the T -count, based on the effective application of “spider nest identities”: easily recognised products of parity-phase operations which are equivalent to the identity operation. We demonstrate the effectiveness of such techniques by obtaining improvements in the T -counts of a number of circuits, in run-times which are typically less than the time required to make a fresh cup of coffee.
Niel de Beaudrap, Xiaoning Bian and Quanlong Wang